Slew rate limited output buffer with bypass circuitry

摘要

An output driver stage for an integrated circuit device includes slew rate control on the final logic gate. Slew rate control is provided by resistors located in the power supply path for the gate. A switch is connected in parallel across the resistor, and can be used to short the resistor to disable or reduce slew rate limiting. The switch is connected to another location within the output circuitry, and disables or reduces the slew rate limiting resistor during a portion of the switching cycle. This provides for slew rate limiting during a portion of switching when it is most needed, and disables it when slew rate limiting is not required.