Semiconductor memory device equipped with sense amplifier circuit which eliminates a transient pulse at an output data terminal

摘要

A sense amplifier circuit incorporated in an electrically programmable read only memory device comprises a differential amplification stage operative to develop a differential voltage level indicative of a read-out data bit for producing a large differential voltage signal, and an output stage having an output inverter variable in threshold level and responsive to the large differential voltage signal for producing an output data signal, and a controller responsive to the output data signal indicative of a previously accessed data bit for varying the threshold level of the output inverter so that the output inverter never produces a transient pulse between sequentially accessed data bits identical in logic level.