| 摘要 |
PCT No. PCT/EP93/02496 Sec. 371 Date Mar. 30, 1995 Sec. 102(e) Date Mar. 30, 1995 PCT Filed Sep. 15, 1993 PCT Pub. No. WO94/08292 PCT Pub. Date Apr. 14, 1994A duplicate control and processing unit for telecommunications equipment consisting of two identical control units connected together is described. Each control unit (UC0, UC1) comprises a processing unit (UP0, UP1) which can be active or on standby, a peripheral data random access memory (RAM) for data processed during operation, and several peripheral circuits connected to the rest of the equipment. An EPROM (erasable programmable read-only memory) (CCL0, CCL1) in each processing unit contains the copy selection firmware. The data RAM and the peripheral circuits include a respective double gate access circuit (ACC0, ACC1) which allows selective access to the active processor only. The latter performs the writing cycles synchronously on both the duplicate data RAMs, allowing fast recovery of the operative synchronism by the standby processing unit, after switching due to failure of the active processing unit (FIG. 2). |
