| 摘要 |
A memory circuit (10) in which redundant cell groups are located in a second memory bank (14; 88) to replace any defective cell groups present in a first memory bank (12; 86). Each bank has its own address decoders (16, 18; 90, 92, 94, 96) and read/write circuits. When an address corresponding to a defective cell group is received, the first bank is enabled as usual, while a fast logic circuit (40; 100) enables the second bank, so that both banks are simultaneously enabled. A signal (32; 102) is transmitted by the logic circuit to an output selector (20; 98) where data from a redundant cell group in the second bank is selected for output (34; 84). The time needed to detect an address corresponding to a defective cell group, is masked by the longer time required by the decoders and sense amplifiers of the respective banks. |
