| 摘要 |
<p>PURPOSE:To attain a power saving by detecting a substantial stopping state in which the program processing of a small loop is repeated by a CPU, and the activation of a substantial work is waited. CONSTITUTION:An address storage and comparator circuit 4 is cleared, operated in an address storage mode only in a learning time Tx, and an address block to which an access is performed by the CPU within the time Tx is stored in the address storage and comparator circuit 4(learning address). Next, the timer of a monitor time Ty set according to the learning time Tx is started, the address storage and comparator circuit 4 is operated in an address comparison mode, and whether or not the access is performed to the address except the learning address by the CPU within the time Ty is monitored by the timer of the time Ty. Then, when the state in which the access is not performed to the address except the learning address within the time Ty is detected, the possibility of the substantial stopping state is judged to be large. Then, a switching circuit 53 is switched, and the CPU is operated in a power saving mode by a clock signal from a low speed clock generating circuit 52.</p> |
