发明名称 HIGH-SPEED PRESCALER CIRCUIT
摘要 PURPOSE:To generate clocks at desired division ratio with high accuracy without an error with inexpensive constitution by dividing clocks at such a dividing ratio that a low-speed counter can count with one high-speed counter, and counting high-speed clocks which include fractions with another high-speed counter. CONSTITUTION:An initial division prescaler 14 counts the reference clocks (at high speed) of high frequency f0, for example, the reference clocks of 24MHz being outputted from an oscillator 12 by the number of clocks at the specified division ratio, for example, twelve clocks, and outputs the initial division clocks of, for example, 2MHz, being divided to 1/2. A low-speed R counter 16 counts this initial division clocks by R clocks, and a high-speed Q counter 18 counts the high-speed reference clocks of fractions being not counted with the R counter 16 by Q clocks. Accordingly, a high-speed prescaler circuit 10 can generate clocks for motor drive of 1/N being divided at division ratio N from the high- speed reference clocks of f0 (24MHz).
申请公布号 JPH0690580(A) 申请公布日期 1994.03.29
申请号 JP19920237164 申请日期 1992.09.04
申请人 FUJI PHOTO FILM CO LTD 发明人 TAKAMORI TETSUYA
分类号 H02P29/00;H02P5/00;H03L7/197 主分类号 H02P29/00
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