Semiconductor memory device, e.g. SRAM with high read=out rate - with controlled potentials applied to bit line pair during active status of address change identification signal

摘要

The memory device has a pair of bit lines (BL,BL) coupled to each of the memory cells (11,12,...), the latter selected via a memory cell selection device (101) in response to received address signals (AD). A read-out data output device (5) responds to the potential difference across the bit line pair to provide a corresponding read-out value, used to determine the potentials applied to the 2 bit lines during the active status of an address change identification signal (S7). Pref. a voltage with a higher level is supplied to the bit line on the lower potential side and a voltage with a lower level is supplied to the bit line on the higher potential side. ADVANTAGE - Increased access speed for static random access memory.