| 摘要 |
A logical circuit (26) for measuring the delay of a semiconductor device is formed substantially in not a logical circuit region (14) but its peripheral region (12). A plurality of inverter gates (261-26n) configuring the logical circuit (26) and wirings between those gates (GL1-GLn) are incorporated in the region (12) and along two boundaries (27a, 27b) of the four boundaries between the peripheral region (12) and the logical region (14), the boundaries (27a, 27b) corresponding to two sides (10a, 10b) of a chip (10) respectively. Thereby, the variation of the delay time of the logical circuit can be suppressed and the highly reliable estimation of the operating speed relative to the logical circuit block of a semiconductor device is possible. <IMAGE> |
