MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof

摘要

In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through. As for the sidewall spacer of the nMOS transistor, its film thickness is selected to effectively restrain hot carrier effect in the vicinity of the drain and restrain degradation of current handling capability due to parasitic resistance to the minimum.