| 摘要 |
A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current in the current terminal (5) is mirrored to the PMOS transistor (P1). During the hold interval the current of the PMOS transistor is mirrored to the current terminal. The mirroring is effected by means of two NMOS transistors (N1, N2) and one reversing switch (S2), which reverses the input and output of the current mirror circuit between the sample intervals and the hold intervals. The current mirror circuit (N1, N2) and the PMOS current source (P1) collectively behave as a current sink which is insensitive to the substrate voltages which are caused by the body effect.
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