| 摘要 |
<p>PURPOSE:To secure a sampling margin 100% without limiting a sampling range with respect to the phase change even when a phase is considerably changed by adding a prescribed waveform generating means. CONSTITUTION:When data are received by a data receiving circuit 1, a violation detection circuit 3 detects the violation of a received waveform, and an F-bit detection circuit 4 detects an F-bit change point after the detection. An L-bit identification circuit 15 of a waveform generating circuit 2 identifies the L bits of the frame of a delayed phase so as to compensate output frame phases between terminals due to the extended passive bus, etc., of a connecting form according to the CCITTI-430, no clock is outputted through a clock preparing circuit reset signal line 18 for clamping the output of a clock preparing circuit 6 until the L bits are not identified, and only the data bit is outputted to a second count circuit 17 and delayed. With this delay, when a slice level is high, it is corrected 100% by preventing duty from being decreased, and phase difference between positive and negative directions or in a zero value code can be matched by a phase matching circuit 23 in the next step.</p> |
