| 摘要 |
PURPOSE:To design a miniaturized semiconductor integrated circuit device, in a short time, wherein the effect of noise arising from the coupling capacitance between the clock signal wiring and other signal wiring is reduced and a high noise margin and operational stability are thereby provided. CONSTITUTION:A macro cell 1a, for CAD system, is so constituted that a clock signal line 6a is placed between VDD power supply lines 4 and 4a and thereby shielded. Use of a macro cell with a clock signal line 6a shielded, like the basic macro cell 1a, maintains a low coupling capacitance between the clock signal line and other signal lines formed in the wiring region, even in CAD. |
