| 摘要 |
PURPOSE:To provide the synchronous type SRAM which has a small number of terminals and can operate at a high speed. CONSTITUTION:While (m) external terminals ADDk/Dink are assigned as common terminals to which (m) bits in an (n)-bit address ADD and (m)-bit write data Din are supplied on a time-division basis, (n-m) external terminals are assigned as address terminals ADDk for the remaining (n-m) bits of the address ADD. In response to the rising of a clock signal CLK, storage registers 1 and 7 input the address ADD from the common terminals ADDk/Dink and address terminals ADDk and addresses a memory array 4 with this address ADD. Consequently, data are read out of the memory array 4 in read mode. In write mode, on the other hand, a storage register 2 inputs write data Din supplied to the external terminals ADDk/Dink in response to the falling of the clock signal CLK and writing circuits 8 and 9 writes the write data Din supplied from the storage register in the addressed position of the memory array 4. |
