| 摘要 |
PURPOSE:To miniaturize a circuit and to accelerate a response speed by connecting the source follower output of nMOS to common output and generating the maximum value of the input of the respective nMOS at the common output. CONSTITUTION:This maximizing circuit is composed by parallelly connecting the plural nMOS T1-T3 and input voltages (x)-(z) are inputted to the nMOS T1-T3. Also, the respective nMOS T1-T3 are provided with the source follower output D1-D3 and the respective output D1-D3 are connected to the common output D0. Then, as the independent characteristics of the respective nMOS T1-T3, output equal to the input voltage is generated at a source, D1=(x,) D2=(y) and D3=(z). In this case, when (x)>(y) and (x)>(z), the nMOS T1 is D1=(x) and the source voltages of the nMOS T2 and T3 are higher than gate voltages. Thus, the nMOS T2 and T3 are interrupted and D1 appears in D0 as it is. Even when (y) or (z) is the maximum, the maximum input voltage similarly appears in D0. |
