| 摘要 |
PURPOSE:To execute an efficient cache flash access by omitting a useless table walk. CONSTITUTION:An address generating unit 12 generates a logical address being a cache flash object. A D-TLB 14a receives this logical address through a data bus 13a, executes a physical address conversion, and also, outputs a hit/mishit signal. In the same way, an I-TLB 14b receives this logical address through an instruction bus 13b, executes the physical address conversion, and also, outputs the hit/mishit signal. In accordance with the hit/mishit signal from each TLB, in the case one of each TLB is an erroneous, multiplexes 16a and 16b supply the physical address of the other TLB to a D-CACHE 15a and an I-CACHE 15b. |
