| 摘要 |
<p>PURPOSE:To maintain the easiness of designing based upon a complete synchronous system and to enable the use of a high clock frequency as to the semiconductor integrated circuit which uses deep submicron technology. CONSTITUTION:Respective modules which constitute the semiconductor integrated circuit are designed by dividing the integrated circuit designed on the basis of the completely synchronous system into plural internally synchronous type logic circuits 1a and providing each of the divided synchronous type logic circuits with an FIFO memory 1b as an input buffer inputting and temporarily storing process data from its precedent stage and a clock detecting circuit 1c which inputs a clock from its precedent stage in order according to process order and distributes the clock after a clock with maximum delay arrives. complete synchronism is obtained in each module and the respective modules are asynchronous with one another. Therefore, the clock skew which determines the limit of an operation frequency depends upon the skew quantity in each module 1 and is not affected by the large clock skew when the clock is distributed to the whole integrated circuit.</p> |
