| 摘要 |
<p>PURPOSE:To enable the same judge processing as in the generating source and to prevent erroneous judgement by providing a shift register to delay an operating system signal just for one cycle of a transfer signal. CONSTITUTION:A '0' system fault detection circuit 1 outputs a '0' system ALM signal 11, in which a '0' system is abnormal or normal, and a '1' system fault detection circuit 2 outputs a '1' system ALM signal 12 in which a '1' system is abnormal or normal. Corresponding to the signals 11 and 12, a system tuning circuit 3 turns the normal system to an operating system according to the selection algorithm and outputs a selected operating system signal 13. Next, the operating system signal 13 is inputted to a shift register 4 and delayed here just for one cycle of the transfer signal. The operating system signal outputted from the shift register 4, signals 11 and 12 and another information signal 14 are multiplexed to the relevant time slot of the frame of a transfer signal 15 and outputted as the transfer signal 15. Thus, fault information and operating system information can be judged within one cycle of the transfer signal while being paired each other.</p> |
