THIRD GROUP FRAME SYNCRONIZING CIRCUIT

摘要

For effective sub-frame detection, this circuit employs a parallel detection method in which the movement of max. 4 bits is possible at a time, and comprises: a counter unit (1) to make timing and control signal for synchronization; a patten comparator (2) to compare a four bit consecutive sequence with a sub-frame pattern; a bit moving signal generater (4) to generate control signal for moving bits; a synchronization state detector (3) to transfer patterns from a synchronized state into asynchronized state if it detects consecutive error bit patterns, transfer them to the synchronized state if it detects 16 consecutive good pattterns.