| 摘要 |
When data read out from a memory cell array is output to an external device through an output buffer, a first and a second address transition detector generate a first read control pulse signal and a second read control pulse signal in response to a change in an address signal. An operation for reading out data is controlled using the first and second read control pulse signals, such that when noise generated by a change in power source potential, due to a change in output, causes a possible detected change in the address signal, the first and second address transition detectors control the output buffer so erroneous operation is prevented.
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