| 摘要 |
An input signal composed of a predetermined total number of symbols is supplied to a series circuit of delay units. The input signal and delayed output signals from the delay units are multiplied by coefficients, and the products are added into an equalized output signal. The supplied input signal is transmitted, successively in normal, opposite, and normal directions, through a predetermined number of delay units corresponding to a unit number of symbols which is smaller than the predetermined total number of symbols to delay the input signal successively with those delay units. Each time the input signal is transmitted in the series circuit in one of the directions, an amplitude error of the equalized output signal is detected. In order to minimize the amplitude error, coefficients by which to multiply the input signal and the delayed output signals are calculated depending on the detected amplitude error. Alternatively, the input signal is divided into a plurality of blocks each composed of a predetermined number of symbols, and supplied to the series circuit to produce an equalized output signal of each of the blocks. An error signal is calculated which is composed of the sum of squares of differences between the equalized output signals and a reference signal. The coefficients are calculated depending on the rates of change of the error signal relative to the coefficients.
|
