| 摘要 |
PURPOSE:To compose a CMOS logical circuit capable of a low voltage operation and operating at high speed by low power consumption. CONSTITUTION:The (n)-channel MOS transistor 12 of high current driving force is connected between a low potential power source and an output terminal, and a (p)-channel MOS transistor 13 and a resistance 14 with a function making the potential of the gate of the transistor 12 and the low potential power source nearly equal, etc. are connected between the gate terminal of the transistor 12 and a high potential power source. The (n)-channel MOS transistor 12 of the high current driving force is used for an output buffer and delay caused by charging/discharging to the gate of the (n)-channel MOS transistor 12 and a capacity component relating with a low density drain layer is reduced so as to quicken a CMOS logical gate favorable to the low voltage operation. |
