发明名称 UP/DOWN COUNTER
摘要 PURPOSE:To speed up carry generating operation and to accelerate a microcom puter or the like including an up/down counter as a general register with an up/down function. CONSTITUTION:A synchronizing up/down counter is constituted of a register REG for selectively inverting respective bits in accordance with their corresponding carry signals C0 to C31, a count-up carry generating circuit CPCG for generating count-up carry signals U0 to U30 at the time of receiving the non-inverted output signals Q0 to Q30 of respective bits of the register REG, a count-down carry generating circuit CDCG for generating count-down carry signals D0 to D30 at the time of receiving the inverted output signals QB0 to QB30 of respective bits of the register REG, and a carry selector CSEL for selectively transmitting a count-up or count-down carry signal to the register REG as the carry signals C0 to C31 in accordance with a count-up control signal CU or a count-down control signal CD.
申请公布号 JPH0667850(A) 申请公布日期 1994.03.11
申请号 JP19920240102 申请日期 1992.08.18
申请人 HITACHI VLSI ENG CORP 发明人 HONDA SHIGERU
分类号 G06F7/507;G06F7/50 主分类号 G06F7/507
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