发明名称 |
METHOD FOR OPERATING PROCESSOR OF TYPE INCLUDING BUS UNIT AND EXECUTING UNIT, CENTRAL PROCESSING UNIT, COMPUTER SYSTEM AND CLOCK CONTROL DEVICE CIRCUIT |
摘要 |
<p>PURPOSE: To provide the clock controller circuit saving power of a high performance microprocessor. CONSTITUTION: In this invention, when an execution unit 12 or an ALU cannot use data, two logic gates and one flip-flop are used to disable a clock signal to the execution unit 12 or the ALU. When a memory device, an I/O or an internal cache cannot provide data or an instruction to the execution unit 12, a sleep mode or a clock idle mode is provided to the execution unit 12. A clock controller circuit 26 gates the clock signal to a logical high level to disable the clock signal The clock controller circuit 26 stops the clock signal in response to a data use disable signal from a bus unit and a data request generating signal from the execution unit 12.</p> |
申请公布号 |
JPH0667768(A) |
申请公布日期 |
1994.03.11 |
申请号 |
JP19930152386 |
申请日期 |
1993.06.23 |
申请人 |
ADVANCED MICRO DEVICDS INC |
发明人 |
JIEEMUSU AARU MAKUDONARUDO |
分类号 |
G06F1/04;G06F1/32;G06F9/38;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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