| 摘要 |
<p>PURPOSE:To generate a clock signal synchronously with an input clock signal without being affected by reset by using a frequency divider to divide an output of a voltage controlled oscillator. CONSTITUTION:An output frequency divider 6 having the same function as that of a feedback frequency divider 4 is provided on the output side of a voltage controlled oscillator 3 and an output clock is outputted from the output frequency divider 6. A phase jump takes place when a device is selected at a host station or the like. When the phase of the input clock is jumped and a phase difference between the input clock and a feedback clock is shifted at the outside of a window width, a window processing unit 5 detects it to reset the feedback frequency divider 4. A phase jump takes place in the feedback clock outputted from the feedback frequency divider 4 and traces to the phase jump of the input clock quickly. Thus, the clock signal synchronously with the input clock is obtained by frequency-dividing the output of the voltage controlled oscillator 3 by the output frequency divider 6.</p> |
