Clock synchronisation for received digital signal - using frequency divider reset by received digital signal, providing clock signal for sampling stage

摘要

A resettable frequency divider (2) is operated at a frequency which is a multiple of the received digital signal (DS); its resetting input (4) being supplied with a resetting pulse (RS) derived from the latter via a flank detector (5, 6). The frequency divider provides a clock signal for a sampling stage (8) receiving the digital signal (DS), at its divider output (3), at half the digital information step length. Pref., the flank detector uses an Exclusive-OR gate, or an Exclusive NOR gate with a timing element (6) across its inputs. ADVANTAGE - Provides synchronisation at high data rate with reduced circuit complexity.