Pulse width modulator with temporary memory - has pulse width data input bus, with data inversion and clock pulse signal counter

摘要

The memory (10) temporarily stores pulse width data fed via a bus and inverted, the data determining the pulse width. The counter (20) handles a clock pulse signal (CK) in response to an external pulse width modulation release signal (RE). A comparator (30) deals with a number of logic 0-bits of the inverted pulse width data of the memory and logic 1-bits of the counter data. It transmits a high level signal, when the number of the logic 0-bits is higher, or equal w.r.t. the logic 1-bits. It transmits a low level signal in a reverse instance. An output device (40) blocks the comparator output signal and transmits a pulse width modulation signal (PWMO). USE/ADVANTAGE - For modulating input signals into desired pulse signals, with simple design, high processing speed and easy integration in single chip.