| 摘要 |
<p>PURPOSE:To generate a clock with high synchronizing accuracy and to facilitate polyphase clock and the revision of its output mode by generating four kinds of clocks with the same frequency but different phase so as to generate a biphase clock synchronously with an external phase reference signal. CONSTITUTION:The clock generating circuit 20 generates four kinds of clocks F1-F4 having the same frequency but different phase. A FF 23 latches the clocks F1-F4 in the application timing of an external phase reference signal PS simultaneously. A conversion table LUT 24 receives a latched data as an address and converts the data into the selection information to select any two- kind of clocks having the phase closest to that of the signal PS among the clocks F1-F4. A FF 25 latches the conversion output data of the LUT 24 simultaneously based on a signal DPS being the result of delay given to the signal PS by a required value by a delay line 26. One kind of clocks designated by a selection data D1 or D2 outputted from the FF 25 is selected at any time among the clocks F1-F4 by selectors 27, 28. The selecting mode is set logically so as to be made coincident with the clock designation mode by the selection information of the LUT 24.</p> |
