发明名称 Multi-level memory cell with increased read-out margin
摘要 A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.
申请公布号 US5293563(A) 申请公布日期 1994.03.08
申请号 US19910807054 申请日期 1991.12.12
申请人 SHARP KABUSHIKI KAISHA 发明人 OHTA, YOSHIJI
分类号 G11C11/56;(IPC1-7):G11C7/00;G11C11/40 主分类号 G11C11/56
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