| 摘要 |
A first test mode signal generating circuit detects, at a timing at which a row address strobe signal changes from an inactive level, to an active level that a column address strobe signal and a write control signal are at an active level to generate an active first test mode signal. A control signal generating circuit detects, during a period in which the row address strobe signal is at the active level, that the column address strobe signal changes from an active level, through an inactive level, and to the active level again to generate an active control signal. A second test mode signal generating circuit generates an active second test mode signal when the first test mode signal and the control signal are at the active level. The first test circuit tests a memory circuit in response to output of the active first test mode signal, and a second test circuit tests the memory circuit in response to output of the active second test mode signal. |
