Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order

摘要

Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order. The test of a smallest addressable unit of a storage medium occurs completely and quickly in an optimum manner. To this end, a test procedure based on parity formation using at least first and second test patterns is used, wherein the effect of a bit error for a test pattern is transferred into the next test pattern. A combination of bit errors when checking this test pattern is thus recognized, derived from the addition of bit errors that appeared separately in the first and second test patterns.