| 摘要 |
A digital signal processor with a built-in dual-port RAM and a bypass signal path for transferring data without the intervention of any bus which is extended between the two ports of the data RAM, whereby in the course of multiply-and-add processing necessary for filter processing, sampling data items to be read out of a predetermined address of the data RAM can be transmitted to an internal bus and can simultaneously be written into the next address of the data RAM to be shifted thereto, in one memory cycle of the data RAM.
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