发明名称 MULTIIPROCESSOR SYSTEM
摘要 PURPOSE:To prevent runaway of a processor by causing a master processor to detect rapidly anomaly of a slave processor. CONSTITUTION:Master processor 1 sets a start instruction and character information to a print buffer and sends an interrupt signal to slave processor 2 to start the count operation of a time supervisory timer. In case that end information from slave processor 2 is not received after a set time from start of the time supervisory timer, master processor 1 sends a reset signal to slave prcessor 2. When the reset signal is inputted, slave processor 2 becomes the initial state. Master processor 1 decides time-out as the first or the second; and in case of the first time-out, master processor sets the start instruction and character information to the print buffer again and sends the interrupt signal to slave processor 2. When time-out occurs again, slave processor 1 resets slave processor 2.
申请公布号 JPS55103618(A) 申请公布日期 1980.08.08
申请号 JP19790010898 申请日期 1979.02.01
申请人 FUJITSU LTD 发明人 YANAGISAWA TSUTOMU;YAMAMOTO HARUMITSU
分类号 G07G1/14;G06F3/00;G06F11/30;G06F13/00;G06F15/16 主分类号 G07G1/14
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