发明名称 Zone-segregated circuit for the testing of electrically programmable memory cells
摘要 To reduce the number of connections in an electrically programmable memory circuit, a device for the testing of the memory cells is proposed. The test consists in the reading of the current that goes through the cells to which access is had in reading mode. The testing device no longer uses specific testing connections between the cells and the corresponding input/output pins but the operational connections of the reading mode, between the reading amplifiers and the input/output buffers, in short-circuiting the input and the output of the reading amplifiers located in a zone close to the memory cells and the input/output buffers located on the peripheral zone, close to the input/output pins. The means to short-circuit the amplifiers and the buffers are respectively located in a zone close to the memory cells, and in the peripheral zone.
申请公布号 US5291448(A) 申请公布日期 1994.03.01
申请号 US19910718627 申请日期 1991.06.21
申请人 SGS-THOMSON MICROELECTRONICS, S.A. 发明人 CONAN, BERTRAND
分类号 G11C29/50;(IPC1-7):G11C29/00 主分类号 G11C29/50
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