| 摘要 |
A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least significant bit, as a function of the state of the first pair of dummy carry signals generated for the least significant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least signficant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least significant bit pair. Sum generators associated with each bit pair choose between the selected dummy sum signals from the first and second dummy select chains in accordance with the state of the carry-in signal associated with the least significant bit pair. Carry generators associated with each bit pair choose between the first and second pairs of dummy carry signals at the ends of the first and second dummy select chains, again in accordance with the state of the carry-in signal associated with the least significant bit pair.
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