| 摘要 |
System for effectuating equiponderant access of processors to common resources comprising n equiponderant processors and n coupling blocks and access blocks, characterized in that each l-th access block (UD1) comprises two NAND logical elements or logically equivalent elements (NAND11, NAND21), whereas one input of the first and of the second logical element of the l-th access block (UD1) is connected to the common resources access demand signal line (BR1) of the l-th processor (P1), the output of the first logical element (NAND11) is connected to the second input of the second logical element (NAND21) and to the switch-on signal line (BE1) connected to the l-th coupling block (US1) and to the inputs of the first logical elements of all remaining access blocks, whereas the remaining inputs of the first logical element (NAND11) of the l-th access block (UD1) are connected through the switch-on signal lines (BE1 .BE1-1, BE1+1, .BEn) to the outputs of the first logical elements of all remaining access blocks, and the output of the second logical element (NAND21) of the l-th access block (UD1) is connected to the l-th processor (P1) through the ready or stop operations of the l-th processor signal line (RDY1).<IMAGE>
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