| 摘要 |
PURPOSE:To provide a WPLL circuit prevented from generating malfunction due to the missetting of an external C bit. CONSTITUTION:An fs information forming circuit 16 consisting of an FV converter 17 for converting the sampling clock of the 1st PLL or its frequency- divided output into voltage and a window comparator 18 for comparing the output voltage is used instead of an external C-bit interface to constitute the WPLL circuit. Consequently the WPLL device capable of normal operation without generating mismatch between a practical sampling clock and fs information can be obtained. |
