发明名称 DATA TRANSMISSION SYSTEM AND COMMUNICATION CONTROLLER
摘要 <p>PURPOSE:To shorten the transmission delay time in which transmission data passes in a communication controller for connection of a computer to a network. CONSTITUTION:A direct memory controller (DMAC) 40 in a communication controller 2 is provided with a means which makes an interim report at an arbitrary timing designated by a local processor 70. The local processor 70 is provided with a means which calculates the timing, when under-run does not occur during data transmission to a network 3, based on the difference between the speed of data transfer from a main memory 20 in a computer 1 to a buffer memory 50 and the network transmission speed, a means which gives this timing to the DMAC 40 as the interim report timing, and a means which synchronizes the completion of protocol processing and the interim report from the DMAC 40 to start a memory controller (MAC) LSI 60. Thus, data transmission to the network is started before a one-packet portion of data to be sent to the network is completely transferred from the main memory in the computer to the buffer memory in the communication controller.</p>
申请公布号 JPH0653994(A) 申请公布日期 1994.02.25
申请号 JP19910285975 申请日期 1991.10.31
申请人 HITACHI LTD 发明人 YOKOYAMA TATSUYA;HIRATA TETSUHIKO;MIZUTANI MIKA
分类号 G06F13/00;G06F13/38;H04L12/801;H04L12/875;H04L12/911;H04L13/08;H04L29/08;(IPC1-7):H04L12/56 主分类号 G06F13/00
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