| 摘要 |
The device includes memories (11,12,13,14) for improving the access time of the block reading and writing, a control signal line (30) for controlling the read and write signal and access signal, an address bus (29) for allocating memories (11,12,13,14) address, a control means (31) for driving the buffer and memory control signals, and buffer means (15,16,17,18) for latching the data by the buffer control signal. The performance of the system is improved by the block reading and writing action in the cache-process system.
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