| 摘要 |
PURPOSE:To prevent a malfunction caused by an error on the midway of a transfer in a digital signal processor which is constituted of an instruction RAM and operated by receiving a program with a data transfer a host CPU. CONSTITUTION:The processor is provided with a host CPU interface block part 1 for receiving a program from a host CPU 6 and provided with an instruction RAM 2 for storing the program. Also, the processor is provided with an instruction decoder 3 for executing the program, a program counter 4, an arithmetic processing part 5, etc., and moreover, provided with an instruction address register part 7 for determining the address of the instruction RAM 2 separately from an instruction executing cycle of the digital signal processor 20 in order to compare the contents of the instruction RAM 2 and the program which the host CPU 6 has, and provided with a comparison result output part 8 for comparing the data outputting the result of comparison. |
