AGC CIRCUIT PROVIDED WITH NONLINEAR GAIN FOR PLL CIRCUIT

摘要

PURPOSE: To provide a reformed device and a method for reducing errors in the stationary state of a PLL(phase-locked loop) circuit. CONSTITUTION: A circuit and a method for generating the drive signal, having a frequency synchronized with a reference frequency signal are provided. This circuit has a PLL circuit 10, possessing a motor 102 and a circuit for generating the signal having frequency proportional to the velocity of the motor 102. A phase detector 11 generates an interval signal proportional to the phase difference between the motor velocity signal and the reference frequency signal. The first phase difference measuring circuit generates the first voltage output signal in the first gain proportional to the phase difference, in the case that the period of the phase detector signal is shorter than a specified time. The second phase difference measuring circuit generates the second output signal in the second gain, in case that the period of the phase detection signal is larger than the specified time. The first and second output signals are added and moreover they are applied to it so as to control the speed of the motor 102.