| 摘要 |
<p>PURPOSE:To remove an useless waiting time such as a margin time and to increase a speed for reading data by deciding the latch timing of a flip-flop corresponding to the real ascertaining time of a sense amplifier. CONSTITUTION:This device is provided with sense amplifiers 5a1-5d1 for reading the contents of memory cells 2a-2d specified by address signals A0-A18 and a timing deciding means 10 deciding a timing for taking the outputs of the sense amplifiers out of the chips. The first dummy part 11 in the constituting elements of the timing deciding means 10 is provided with a dummy memory cell having the same composition or the same input/output delay as that of the memory cells and a second dummy part 12 is provided with a dummy sense amplifier having the same composition or the same input/output delay as that of the sense amplifier. Also, a signal generating part 13 is provided and the timing for taking the outputs of the sense amplifiers 5 a1-5ad out of the chips based on the time when the output of the dummy sense amplifier is ascertained.</p> |
