发明名称 PHASE LOCKED LOOP OSCILLATOR
摘要 PURPOSE:To shorten a lock-up time by quickly raising a low pass filter (LPF) by a comparator during a prescribed period after impressing power supply voltage, and separating the LPF after the lapse of the prescribed time. CONSTITUTION:A frequency divider 12 divides the frequency of an output from a variable voltage control type oscillator 11 and a reference signal generator 13 outputs a signal with reference frequency. A phase detector 14 detects a phase difference between an output signal from the frequency divider 12 and a reference signal from a reference signal generator 13 by mutually comparing both signals and generates an output corresponding to the phase difference. The LPF 15 converts the output of the detector 14 into DC control voltage by smoothing the output as control voltage for the oscillator 11. A comparator 16 compares the control voltage obtained from the LPF 15 with reference voltage VR1. When the voltage of a terminal 21 is lower than the reference voltage VR1, a capacitor in the LPF 15 is quickly charged through the comparator 16. After the lapse of the prescribed time, switches SW1, SW2 are switched.
申请公布号 JPH0653824(A) 申请公布日期 1994.02.25
申请号 JP19920203501 申请日期 1992.07.30
申请人 NEC CORP 发明人 MATSUMURA EIICHI
分类号 H03L7/093;H03L7/10 主分类号 H03L7/093
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