发明名称 TEST PATTERN GENERATING METHOD FOR SYNCHRONOUS SEQUENTIAL CIRCUIT
摘要 PURPOSE:To provide the test pattern generating method for a synchronous sequential circuit for enhancing a fault detection ratio, executing a test pattern generation processing and shortening a test time. CONSTITUTION:In a step 10, by connecting a sequence for realizing a state transition extending from an initial state of the state transition to an erroneous transition destination state by using a state transition description and a sequence for discriminating a normal transition state and an erroneous transition destination state, a pattern sequence for detecting a specific transition fault is generated, and in a step 20, an extended pattern sequence for detecting other transition fault is generated in a state that a value outputted from a storage element part to a combination circuit part at every pattern corresponding to each state subjected to transition by the pattern sequence remains fixed. In a step 30, a pattern is synchronized with a clock and given successively as an external input to the combination circuit part and by throwing in the clock, an external output is observed, and thereafter, by applying the extended pattern one after another in a state that the clock remains fixed, the external output is observed.
申请公布号 JPH0652005(A) 申请公布日期 1994.02.25
申请号 JP19920203618 申请日期 1992.07.30
申请人 FUJITSU LTD 发明人 NAKADA TSUNEO
分类号 G06F11/22 主分类号 G06F11/22
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