发明名称 MEMORY HOLD CONTROLLER
摘要 <p>PURPOSE:To simplify the device and to extend the backup time of an SRAM or the like by connecting a low active reset signal from a power supply voltage monitor device to the input terminal of the SRAM and simultaneously connecting a high resistor for pull-down so that this input terminal can be stablized at a ground level in the case of power failure. CONSTITUTION:The low active reset signal is sent from a power supply voltage monitor device 4 to the input terminal of a chip select signal CE of an SRAM 3, a high resistor R2 for pull-down is connected so that the CE input terminal of the SRAM 3 can be stablized at the ground level in the case of power failure, and a resistor R1 is provided to supply a current to a reset line during a system operation. Thus, a gate IC constituting a chip select signal generator can be omitted, the device can be simplified, and the backup time of the memory cell such as the SRAM can be extended.</p>
申请公布号 JPH0651878(A) 申请公布日期 1994.02.25
申请号 JP19920204813 申请日期 1992.07.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MORITA TOMOHIRO
分类号 G06F1/30;G06F12/16;(IPC1-7):G06F1/30 主分类号 G06F1/30
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