| 摘要 |
<p>PURPOSE: To provide a high speed packet switch by providing packet memory means having switch memories and packet output means for plural packet input means. CONSTITUTION: The parallel input packets of one bit and the like by an input shift register are outputted to a parallel/series conversion output means through input parts 202-0 to 202-31, the packet memory means 213-0 to 213-31 having the switch memories 211-0 to 211-31 and output means 219-0 to 219-31. The switches 210-0 to 210-3 are controlled through a switch processor. Thus, the buses among the means 205-0 to 205-31, 213-0 to 213-31, 219-0 to 219-31 do not cross the boundaries of the semiconductor chips of the switches 211-0 to 211-31. Thus, the packet switch which can avoid the electric fault of the bus and which operates at high speed is provided.</p> |
