| 摘要 |
The circuit includes 1,2 CVDM main clock division circuits (21,22) for dividing the 14.7456 KHz into the 283.57 KHz and 245.76 KHz signals, 1,2 ROVM main clock division circuits (24,25) for dividing the 14.7456 KHz into the 139.11 KHz and 101.00 KHz signals, a clear pulse generating circuit (23) for generating the clear signals, a transmitting carrier frequency multuplexer circuit (26) for multiplexing the clock into the TDATA and DVM signals, a FSK signal generating circuit (27) for generating the FSK signals by the clock signal of the MUX to apply to a FSK circuit (28).
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