Clock signal selection circuit

摘要

A clock signal selection circuit includes a delay for delaying a switching control signal to supply a delayed switching control signal. A first selection circuit changes its state between first and second states in response to the switching control signal. A second selection circuit changes its circuit condition between third and fourth states in response to the switching control signal and the output of first selection circuit. The second selection circuit outputs a second clock signal when operated in the third state and inhibits the second clock signal in the fourth state. The first selection circuit supplies the first clock signal when operated in the first state and inhibits the first clock signal from being supplied when operated in the second state in response to the switching control signal and the output of second selection circuit. A third selection circuit transmits the switching control signal to either the first or second selection circuit in response to the delayed control signal.