Frequency division timing circuit employing shunting circuit for inhibiting false reset signals to flip-flop stages,申请号US19630327643-传众专利搜索

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发明名称	Frequency division timing circuit employing shunting circuit for inhibiting false reset signals to flip-flop stages
摘要
申请公布号	US3312835(A)	申请公布日期	1967.04.04
申请号	US19630327643	申请日期	1963.12.03
申请人	BOLKOW GESELLSCHAFT MIT BESCHRANKTER HAFTUNG	发明人	GRASMUCK DIETER
分类号	H03K3/037;H03K21/00	主分类号	H03K3/037
代理机构		代理人
主权项
地址

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