Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory

摘要

A microprocessor system has a bus system for coupling several processing units, each having an appertaining private cache memory and a common main memory. When an address operation of a transaction is executed, a transaction identification number is generated and transmitted on the system bus to all other subscribers together with the fed address of the initiating subscriber. In each subscriber, memory means are provided for storing the transmitted address and the co-delivered transaction identification number. Simultaneously with the assignment of the system bus for further transmissions, the address stored in the memory means are monitored in test means of the subscribers, and after monitoring, a synchronization signal and possibly accompanying signals are set by all subscribers for the abortion or continuation of a transaction. Given continuation with a data operation, an allocation of the data operation to its corresponding address operation can be achieved by return transmission of the associated transaction identification number together with the data to the initiating subscriber, which permits that the sequential order of the data operations sequence is not bound to that of the corresponding address operations.