| 摘要 |
The VISS VASS code detection circuit for VTR wherein, an output of a first flipflop is connected to the input port of a third flipflop via a second flipflop, the output port of the third flipflop via an inverter (111) connects the output of a T flipflop connected to each reset port with clock pulse input port of the T flipflop, the output port of the T flipflop connects a data input port of a forth flipflop with the clock port of the output of the first flipflop, the output port of the forth flipflop is connected to final output port via an inverter (112), thereby removing the need for additional circuit for generating an up signal and down signal of the up-down counter.
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